The minimum feature size of semiconductor integrated circuits has been miniaturized, reaching the minimum feature size for mass production of 32 nm. Thus, more transistors can be integrated now. Such a large-scale integrated circuit is also called a System LSI.
FIG. 19 is a block diagram illustrating the configuration of the System LSI based on the NOC communication. As shown in FIG. 19, the System LSI (also called a System-on-chip: SoC) 40 is generally composed of many functional processing units (Intellectual Property Cores, called IP cores) 41. Due to the recent miniaturization of the minimum feature size, the SoC 40 is structured so that one chip therein can include integrated IP cores 41 for calculation, digital signal calculation (DSP), and memories. The method for providing communication among these IP cores 41 via routers 42 provided in adjacent to the IP cores 41 and based on packet information is called a Network-on-Chip (NoC).
Each IP core 41 in a single NoC operates at the clock frequency of each IP core 41. In other word, each IP core 41 generally operates at a different clock frequency. The communication among the IP cores 41 is performed by synchronous control or asynchronous control without clocks. For example, synchronous control is used in a computer-bus communication. The synchronous control generally has a low degree of design freedom and requires high power dissipation.
In order to solve the above disadvantage in the conventional synchronous control, the communication among the IP cores 41 has been increasingly carried out by asynchronous control (see Patent Reference 1). It is well known that two methods such as a four-phase encoding (see Non-patent References 1 and 2) and a two-phase encoding (see Non-patent References 3 and 4) are used as a typical asynchronous communication protocol.
First, let us explain the four-phase dual-rail encoding (see Non-patent Reference 5). In the four-phase dual-rail encoding, the continuous time-series “data” are distinguished alternately using two kinds of dual-rail codes that correspond to “data” and “spacer”, respectively. The term “phase” means “the number of steps to carry out one data transfer” and the term “rail” means “the number of wires required for transferring one data”.
FIG. 20 illustrates the four-phase dual-rail encoding, wherein (A) illustrates an asynchronous data transfer channel model based on the four-phase dual-rail encoding, (B) illustrates the definitions of codes, and (C) illustrates one data-transmission procedure in a data-transfer protocol based on the four-phase dual-rail encoding.
A four-phase dual-rail code is a one hot code in which two wires x and x′ (see FIG. 20(A)) are allocated with the logical values “1” and “0” to rise any one of the wires to thereby recognize data arrival. The continuous time-series data stream can be recognized by the insertion of the spacer between the codes corresponding to the data (see FIG. 20(B)).
As shown in FIG. 20(C), one data is transmitted in accordance with the following communication protocol based on the four-phase dual-rail encoding as
(1) The transceiver recognizes an acknowledge signal from the receiver, and sends a new data to the receiver.
(2) The receiver detects the new data, and returns an acknowledge signal that the new data has been surely arrived at the receiver.
(3) The transceiver recognizes the acknowledge signal, and sends a “spacer” signal to the receiver.
(4) The receiver detects the “spacer” signal, and returns an acknowledge signal that the “spacer” signal has been surely arrived at the receiver.
As described above, the four-phase dual-rail code requires a set of request-acknowledge procedure for both of data code and spacer code, thus requiring as many as 4 steps to complete a single data transmission (also called completion). Thus, the data transfer requires a long cycle time.
Next, let us explain the two-phase dual-rail encoding (see Non-patent Reference 5).
In the two-phase dual-rail protocol, the “spacer” of the four-phase protocol is omitted for the purpose of providing a higher speed and data called “EVEN” and “ODD” is used.
FIG. 21 illustrates the two-phase dual-rail code, wherein (A) illustrates an asynchronous data transfer channel model based on the two-phase dual-rail encoding, (B) illustrates the definition of the code, and (C) illustrates the procedure for one data transfer in the transfer protocol based on the two-phase dual-rail encoding.
A two-phase dual-rail code is a code in which dual-rail codes, x and x′, are allocated with the logical values “1” and “0” to rise any one of the dual-rail codes to thereby recognize data arrival (see FIG. 21(A)).
The two-phase dual-rail code data has two different definitions of an “odd number” and an “even number” (see FIG. 21(B)). Pieces of continuous data are identified based on alternately arranged codes having difference definitions. The data is defined so that only one of the dual-rail codes, x and x′, changes at a shift from an “odd number” to an “even number” or a shift from an “even number” to an “odd number”. Thus, an effective state can be detected correctly.
As shown in FIG. 21(C), one data transfer in the transfer protocol based on the two-phase dual-rail encoding is performed based on the following procedure.
(1) The transceiver recognizes the inversion of the response signal from the receiver and sends data having a different definition from that of the data to the receiver.
(2) The receiver detects the data having the different definition and sends an inverted response signal to the transceiver.
As described above, the two-phase dual-rail encoding does not require, in contrast with the four-phase dual-rail encoding, the request response processing required due to spacer insertion. Thus, the two-phase dual-rail encoding advantageously requires a procedure of two steps to complete one data transfer.
In recent years, in the four-phase asynchronous communication method, such a link circuit has been designed that uses a four-phase protocol to use a quasi-delay-insensitive logic method (hereinafter referred to as a QDI logic method) to provide the connection between routers (see Non-patent References 1 and 2).
On the other hand, in the two-phase asynchronous communication method, a high-speed asynchronous communication link (see Non-patent Reference 4) has been reported that uses a two-phase protocol (see Non-patent Reference 3). However, the two-phase protocol circuit is disadvantageous in that complicated latch and functional block are required and thus a large area is required, thus causing an increased delay time. Due to this reason, a calculation block such as a router generally uses a four-phase protocol.
An asynchronous protocol converter using a QDI logic method has been suggested (see Non-patent References 6 and 7). A protocol converter is a converter that converts a two-phase protocol to a four-phase protocol or a reverse conversion that converts a four-phase protocol to a two-phase protocol.
FIG. 22 is a block diagram illustrating the configuration of an asynchronous protocol converter 50 using the above QDI logic method. As shown in FIG. 22, the conventional asynchronous protocol converter 50 is composed of: a two-to-four-phase protocol converter 51; a four-phase router 52 connected to this protocol converter 51; a four-to-two-phase protocol converter 53 for converting the four-phase protocol signal output from the four-phase router 52 again to a two-phase protocol signal; and a controller 54.
The four-phase router 52 is configured to include: a routing circuit 52a; an arbitration circuit 52b; and a multiplexer (also may be abbreviated as MUX) circuit 52c. A register 52d is provided between the routing circuit 52a and the arbitration circuit 52b. Similarly, a register 52e is provided between the arbitration circuit 52b and the multiplexer circuit 52c. These registers 52d and 52e are used to increase the communication speed (see Non-patent Reference 1).
FIG. 23 is a timing chart illustrating the operation of a conventional asynchronous protocol converter using the QDI logic method. As shown in FIG. 23, at first, all four-phase signals are low as a spacer. An input phase signal and an output phase signal are a two-phase signal and have the same phase information “even”. When a new two-phase input having the phase information “odd” comes, the input phase signal shifts and acknowledges “enable” to become high. As a result, the two-to-four-phase protocol converter 51 generates the “data” for a four-phase protocol. Then, the four-phase router performs the calculation based on the three functional blocks (i.e., the routing circuit 52a, the arbitration circuit 52b, and the multiplexer circuit 52c). After the calculation by the four-phase router 52, the four-to-two-phase protocol converter 53 outputs a new two phase having the phase information “odd”.
On the other hand, when the completion is confirmed and the output phase signal changes, then “enable” is confirmed again in order to reset the four-phase router 52 to generate a spacer. At the same time, the two-phase input changes. After the four-phase router 52 is reset, the completion is confirmed again. This means the preparation for the protocol conversion of the input signal of the next two phase.
In the case of the conventional asynchronous protocol converter 50, a new two-phase input signal is encoded after all of the functional blocks of the four-phase router 52 are reset by the decoding of the previous two-phase signals in the four-to-two-phase protocol converter 51.
Thus, the cycle time (tcycle—conv) of the conventional asynchronous protocol converter 50 is the sum of the delay time composed of the two-to-four-phase protocol converter (2p->4p) 51, the functional block of the four-phase pipelined router 52 (i.e., the routing circuit 52a, the arbitration circuit 52b, and the multiplexer circuit 52c), the four-to-two phase protocol converter (4p->2p) 53, and the “data” and “spacer” of the controller 54. Therefore, the cycle time (tcycle—conv) can be obtained by the following equation (1).
[Equation 1]tcycle—conv=t2p→4p+k×(tfb—data+tfb—spacer)+t4p→2p+t2p→4p+tcont—data+tcont—data  (1)
In the equation, k denotes the number of the stages of the circuit of the router having a pipelined structure. In the case of the four-phase router 52 with the pipelined structure shown in FIG. 23, k=3 is established.
As described above, when the asynchronous four-phase pipelined circuit (e.g., the four-phase router 52) is used together with the conventional protocol converter, the cycle time (tcycle—conv) increases in proportion to the number of stages of the pipelined circuit.